Publications

Also see my Google Scholar Page.

Book Chapter

  1. T. M. Taha, R. Hasan, C. Yakopcic, and M. R. McLean, “Exploring the Design Space of Specialized Multicore Neural Processors,” Cybersecurity Systems for Human Cognition Augmentation, R. Pino, A. Kott, and M Shevenell (ed), Springer. July 2014.

  2. Invited book chapter: Tanvir Atahary, Tarek Taha, and Scott Douglass, “Hardware Accelerated Mining of Domain Knowledge,” Network Science and Cyber Security, R. Pino (ed), Springer. July 2013.

  3. C. Yakopcic, T. M. Taha, G. Subramanyam, R. Pino, and S. Rogers, “Memristor SPICE Modeling,” in Advances in Neuromorphic Memristor Science and Applications, by R. Kozma, R. Pino, and G. Pazienza (eds), Springer. July 2012.

Journal

  1. C. Yakopcic, S. Wang, W. Wang, E. Shin, J. Boeckl, G. Subramanyam, and T. M. Taha, "Filament Formation in Lithium Niobate Memristors Supports Neuromorphic Programming Capability," Neural Computing and Applications (accepted).

  2. C. Yakopcic, V. Bontupalli, R. Hasan, D. Mountain, and T. M. Taha, “Self-biasing memristor crossbar used for string matching and TCAM implementation,” Electronics Letters (accepted).

  3. P. Sidike, E. Krieger, M. Z. Alom, V. K. Asari, and T. Taha, "A fast single image super-resolution via directional edge guided regularized extreme learning regression," Signal, Image and Video Processing, December 2016.

  4. C. Merkel, R. Hasan, N. Soures, D. Kudithipudi, T. Taha, S. Agarwal, and M. Marinella, "Neuromemristive Systems: Boosting Efficiency through Brain-Inspired Computing", Computer, 49(10), 56-64, Oct. 2016.

  5. M. Z. Alom, P. Sidike, T. M. Taha, and V. K. Asari, "State Preserving Extreme Learning Machine: A Monotonically Increasing Learning Approach," Neural Processing Letters, September 2016.

  6. S. Wang, W. Wang, C. Yakopcic, E. Shin, G. Subramanyam and T. M. Taha, “Reconfigurable Neuromorphic Crossbars Based on Titanium Oxide Memristors,” Electronics Letters, vol. 52, no. 20, pp. 1673-1675, September 2016.

  7. Khader Mohammad, Ahsan Kabeer, Tarek M. Taha, Muhsen Owaida, Mahdi Washha, "Off-chip bus power minimization using serialization with cache-based encoding," Microelectronics Journal, 54(8), 138–149, August 2016.

  8. Tanvir Atahary, Tarek M. Taha, and Scott Douglass, “Parallelized mining of domain knowledge on GPGPU and Xeon Phi clusters,” The Journal of Supercomputing, Volume 72, Issue 6, pp 2132-2156, June 2016.

  9. C. Yakopcic and T. M. Taha, “Model for maximum crossbar size based on input driver impedance,” Electronics Letters, vol. 52 no. 1, pp. 25-27, 2016.

  10. Zahangir Alom, Venkata Ramesh Bontupalli, and Tarek M. Taha “Intrusion Detection Using Deep Belief Network and Extreme Learning Machine”, International Journal of Monitoring and Surveillance Technologies Research, 3(2), 36-58, April-June 2016.

  11. C. Yakopcic, R. Hasan, and T. M. Taha, “Hybrid Crossbar Architecture for a Memristor Based Cache,” Microelectronics Journal, vol. 46, no. 11, pp. 1020-1032, November, 2015.

  12. C. Yakopcic and T. M. Taha, “Determining optimal switching speed for memristors in a neuromorphic system,” Electronics Letters, vol. 51 no. 21, pp. 1637-1639, 2015.

  13. C. Yakopcic, T. M. Taha, M. R. McLean, “Method for ex-situ training in a memristor-based neuromorphic circuit using a robust weight programming method,” Electronics Letters, vol. 51, no. 12, pp. 899-900, 2015.

  14. K. Mohammad, A. Kabeer, T. M. Taha, “On-Chip power minimization using serialization-widening with frequent value encoding,” VLSI Design, 6, January 2014.

  15. C. Yakopcic, R. Hasan, T. M. Taha, M. McLean, and D. Palmer, “Memristor-based neuron circuit and method for applying a learning algorithm in SPICE,” IET Electronics Letters, 2014.

  16. C. Chen and T. M. Taha, “A Communication Reduction Approach to Iteratively Solve Large Sparse Linear Systems on a GPGPU Cluster,” Cluster Computing, Volume 17, Issue 2, pp 327-337, June 2014.

  17. C. Yakopcic, T. M. Taha, G. Subramanyam, and R. E. Pino, “Generalized Memristive Device SPICE Model and its Application in Circuit Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32:(8), 1201-1214, August 2013. This model has been incorporated into the parallel SPICE simulator, XYCE, from Sandia National Labs. See XYCE Dec 2015 release notes about Yakopcic memristor model.

  18. C. Yakopcic, T. M. Taha, G. Subramanyam, R. E. Pino, S. Rogers, “A Memristor Device Model,” IEEE Electron Device Letters, IEEE Electron Device Letters, 30(10), 1436-1438, October 2011.

  19. P. Yalamanchili, S. Mohan, R. Jalasutram, and T. M. Taha, “Acceleration of Hierarchical Bayesian Network Based Cortical Models on Multicore Architectures,” Parallel Computing, 36:(8), 449-468, August 2010.

  20. B. Han and T. M. Taha, “Acceleration of spiking neural network based pattern recognition on NVIDIA graphics processors,” Applied Optics, 49:(101), 83-91, April 2010.

  21. K. L. Rice, T. M. Taha, A. M. Chowdhury, and A. Awwal, “Design and Acceleration of Phase-only Filter Based Optical Pattern Recognition for Fingerprint Identification,” Optical Engineering, vol. 48, November 2009.

  22. A. Awwal, K. L. Rice, and T. M. Taha, “Hardware-Accelerated Optical Alignment of Lasers Using Beam-Specific Matched Filters,” Applied Optics, 48:(27), 5190-5196, September 2009.

  23. C. Vutsinas, K. L. Rice, and T. M. Taha, “A Context Switching Streaming Memory Architecture to Accelerate a Neocortex Model,” Microprocessors and Microsystems, 33:(2), 117-128, March 2009.

  24. A. Awwal, K. L. Rice, and T. M. Taha, “Fast Implementation of Matched Filter Based Automatic Alignment Image Processing,” Optics and Laser Technology, 41:(2), 193-197, March 2009.

  25. K. L. Rice, C. Vutsinas, and T. M. Taha, “A Scaling Analysis of a Neocortex Model Implementation on the Cray XD1,” Journal of Supercomputing, 47:(1), 21-43, January 2009.

  26. K. L. Rice, C. Vutsinas, and T. M. Taha, “Hardware Acceleration of Image Recognition through a Visual Cortex Model,” Optics & Laser Technology, 40:(6), 795-802, September 2008.

  27. T. M. Taha, and D. S. Wills, “An Analytical Model of Superscalar Processor Performance,” IEEE Transactions on Computers, 57:(3), 389-403, March 2008.

  28. S. M. Chai, T. M. Taha, D. S. Wills, and J. D. Meindl, “Heterogeneous Architecture Models for Interconnect Motivated System Design,” IEEE Transactions on VLSI Systems, Special Issue on System Level Interconnect Prediction, 8:(6), 660-670, 2000.

  29. D. S. Wills, J. M. Baker, H. H. Cat, S. M. Chai, L. Codrescu, J. Cruz-Rivera, J. Eble, A. Gentile, M. Hopper, W. S. Lacy, A. Lopez-Lagunas, P. May, S. Smith, and T. Taha, “Processing Architectures for Smart Pixel Systems,” IEEE Journal of Selected Topics in Quantum Electronics, 2:(1), 24-34, 1996.

Conference

  1. T. Atahary, T. Taha, S. Douglass, “Parallelizing Knowledge Mining in a Cognitive Agent for Autonomous Decision Making”, IEEE Computing Conference 2017, July 2017.

  2. Nayim Rahman, Tarek Taha1, Tanvir Atahary, and Scott Douglass, “A Pattern Matching Approach to Map Cognitive Domain Ontologies to the IBM TrueNorth Processor,” IEEE Cognitive Communications for Aerospace Applications Workshop, June 2017.

  3. Nayim Rahman, Tanvir Atahary, Tarek Taha and Scott Douglass. “Cognitive Domain Ontologies on the TrueNorth Neurosynaptic System” IEEE International Joint Conference on Neural Networks, May 2017.

  4. R. Hasan, T. M. Taha, “On-chip Training of Memristor Based Deep Neural Networks,” IEEE International Joint Conference on Neural Networks, May 2017.

  5. C. Yakopcic, S. Wang, W. Wang, E. Shin, G. Subramanyam and T. Taha, “Methods for High Resolution Programming in Lithuim Niobate Memristors for Neuromorphic Hardware,” IEEE International Joint Conference on Neural Networks, May 2017.

  6. C. Yakopcic, Z. Alom and T. Taha, “Extremely Parallel Memristor Crossbar Architecture for Convolutional Neural Network Implementation,” IEEE International Joint Conference on Neural Networks, May 2017.

  7. Md Zahangir Alom, Tarek M. Taha, and Khan Iftekharuddin, "Object Recognition using Cellular Simultaneous Recurrent Networks and Convolutional Neural Network,” IEEE International Joint Conference on Neural Networks, May 2017.

  8. Md Zahangir Alom, Brian Van Essen, Adam T. Moody, David Peter Widemann, and Tarek M. Taha, "Convolutional Sparse Coding on Neurosynaptic Cognitive System,” IEEE International Joint Conference on Neural Networks, May 2017.

  9. Md Zahangir Alom, and Tarek M. Taha, "Network Intrusion Detection for Cyber Security on Neuromorphic Computing System,” IEEE International Joint Conference on Neural Networks, May 2017.

  10. Md Zahangir Alom, Brian Van Essen, Adam T. Moody, David Peter Widemann, and Tarek M. Taha, "Quadratic Unconstrained Binary Optimization (QUBO) on Neuromorphic Computing System,” IEEE International Joint Conference on Neural Networks, May 2017.

  11. R. Hasan, T. M. Taha, C. Yakopcic, and D. Mountain, “High throughput neural network based embedded streaming multicore processors,” IEEE International Conference on Rebooting Computing (ICRC), San Diego, CA, November 2016.

  12. F. Palenzuela, M. Shaffer, M. Ennis, J. Gorski, D. McGrew, D. Yowler, D. White, L. Holbrook, C. Yakopcic, and T. M. Taha, “Multilayer Perceptron Algorithms for Cyberattack Detection,” IEEE National Aerospace and Electronics Conference, July, 2016.

  13. S. Wang, W. Wang, C. Yakopcic, E. Shin, G. Subramanyam and T. M. Taha, “Memristor Devices for use in Neuromorphic Systems,” IEEE National Aerospace and Electronics Conference, July, 2016.

  14. C. Yakopcic, M. Z. Alom, and T. M. Taha, “Memristor Crossbar Deep Network Implementation Based on a Convolutional Neural Network,” IEEE International Joint Conference on Neural Networks (IJCNN), 2016.

  15. R. Hasan, T. M. Taha and C. Yakopcic, “Ex-situ Training of Dense Memristor Crossbar for Neuromorphic Applications,” in the proceedings of the IEEE International Symposium on Nanoscale Architectures, July, 2015.

  16. M. Z. Alom, P. Sidike, V. Asari, T. M. Taha, “State Preserving Extreme Learning Machine for Face Recognition,” IEEE International Joint Conference on Neural Networks (IJCNN), July 2015.

  17. C. Yakopcic and T. M. Taha, “Memristor Based Neuromorphic Circuit for Ex-Situ Training of Multi-Layer Neural Network Algorithms,” IEEE International Joint Conference on Neural Networks (IJCNN), July 2015.

  18. Md. Zahangir Alom, VenkataRamesh Bontupalli, Tarek M. Taha, “Intrusion Detection using Deep Belief Networks,” in the IEEE National Aerospace and Electronics Conference, 2015.

  19. R. Hasan, T. M. Taha, “Memristor Crossbar Based Unsupervised Training,” in the IEEE National Aerospace and Electronics Conference, 2015.

  20. C. Yakopcic, R. Hasan, T. M. Taha, and D. Palmer, “SPICE Analysis of Dense Memristor Crossbars for Low Power Neuromorphic Processor Designs” IEEE National Aerospace and Electronics Conference, June, 2015.

  21. S. Wang, W. Wang, E. Shin, C. Yakopcic, G. Subramanyam, T. M. Taha, “Lithium Based Memristive Devices” IEEE National Aerospace and Electronics Conference, June, 2015.

  22. C. Yakopcic, T. M. Taha, “Ex-Situ Programming in a Neuromorphic Memristor Based Crossbar Circuit” IEEE National Aerospace and Electronics Conference, June, 2015.

  23. R. Uppala, C. Yakopcic, T. M. Taha, “Methods for Reducing Memristor Crossbar Simulation Time” IEEE National Aerospace and Electronics Conference, June, 2015.

  24. C. Yakopcic, T. M. Taha, G. Subramanyam, and R. E. Pino, “Impact of Memristor Switching Noise in a Neuromorphic Crossbar” IEEE National Aerospace and Electronics Conference, June, 2015.

  25. M. Edmonds, T. Atahary, T. Taha, and S. Douglass, “High performance declarative memory systems through MapReduce,” In 16th IEEE ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD), 2015.

  26. T. Atahary, T. Taha, F.Webber, S. Douglass, “Knowledge mining for cognitive agents through path based forward checking”. In 16th IEEE ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD), 2015.

  27. R. Hasan, T. M. Taha, “Memristor Crossbar Based Low Power Intrusion Detection Systems” 17th Int'l Conf. on Computer and Information Technology, 2014.

  28. R. Hasan and T. M. Taha, “Memristor Crossbar Based Programmable Interconnects,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014.

  29. T. M. Taha, R. Hasan, and C. Yakopcic, “Memristor Crossbar Based Multicore Neuromorphic Processors,” IEEE International System on Chip (SOC) Conference, 2014.

  30. R. Hasan, T. M. Taha, “Memristor Crossbar Based Low Cost Classifiers and Their Applications,” IEEE NAECON, 2014.

  31. Y. Qi, B. Zhang, T. M. Taha, H. Chen, and R. Hasan, “FPGA Design of a Multicore Neuromorphic Processing System,” IEEE NAECON, 2014.

  32. V. Bontupalli, R. Hasan, T. M. Taha, “Power Efficient Architecture for Network Intrusion Detection System,” IEEE NAECON, 2014.

  33. W. Wang, C. Yakopcic, E. Shin, K. Leedy, T. M. Taha, and G. Subramanyam, “Fabrication, Characterization, and Modeling of Memristor Devices,” IEEE NAECON, 2014.

  34. C. Yakopcic, T. M. Taha, and R. Hasan, “Hybrid Crossbar Architecture for a Memristor Based Memory,” IEEE NAECON, 2014.

  35. C. Yakopcic, R. Hasan, T. M. Taha, “Tolerance to Defective Memristors in a Neuromorphic Learning Circuit,” IEEE NAECON, 2014.

  36. Raqib Hasan and Tarek M. Taha, “Implementation of Polynomial Classifier Using Memristor Crossbar Circuits,” IEEE International Joint Conference on Neural Networks (IJCNN), 2014.

  37. Raqib Hasan and Tarek M. Taha, “Enabling Back Propagation Training of Memristor Crossbar Neuromorphic Processors,” IEEE International Joint Conference on Neural Networks (IJCNN), 2014.

  38. Chris Yakopcic, Raqib Hasan, Tarek M. Taha, Mark R. McLean, and Doug Palmer, “Memristor Neuron Circuits for Linearly and Non-Linearly Separable Functions,” IEEE International Joint Conference on Neural Networks (IJCNN), 2014.

  39. T. M. Taha, R. Hasan, C. Yakopcic, and M. R. McLean, “Exploring the Design Space of Specialized Multicore Neural Processors,” IEEE International Joint Conference on Neural Networks (IJCNN), 2013.

  40. R. Hasan and T. M. Taha, “On-Chip Routing for Neuromorphic Architectures,” IEEE International Joint Conference on Neural Networks (IJCNN), 2013.

  41. C. Yakopcic, T. M. Taha, G. Subramanyam, and R. E. Pino, “Memristor SPICE Model and Crossbar Simulation Based on Devices with Nanosecond Switching Time,” IEEE International Joint Conference on Neural Networks (IJCNN), 2013. Received IJCNN 2013 BEST PAPER Award

  42. C. Yakopcic and T. M. Taha, “A Novel Memristor-Based Neural Architecture Capable of Perceptron Training Verified in SPICE,” IEEE International Joint Conference on Neural Networks (IJCNN), 2013.

  43. T. Atahary, T. M. Taha, S. Douglass, “Hardware Accelerated Cognitively Enhanced Complex Event Processing,” 14th IEEE ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2013), July, 2013.

  44. T. M. Taha, R. Hasan, C. Yakopcic, and M. R. McLean, “Memory Integrated Neural Network Accelerators,” Neuro-Inspired Computational Elements Workshop, Albuquerque, NM, February 26, 2013.

  45. C. Yakopcic, T. Taha, G. Subramanyam, and R. Pino, “A Generalized Memristor Device Model,” Network Science and Reconfigurable Systems for Cybersecurity Conference, 2012.

  46. T. Taha and S. Douglass, “Hardware Accelerated Mining of Domain Knowledge,” Network Science and Reconfigurable Systems for Cybersecurity Conference, 2012.

  47. C. Yakopcic, T. M. Taha, G. Subramanyam, and S. Rogers, “Memristor-based Readout Integrated Circuits,” SPIE Adaptive Coded Aperture Imaging and Non-Imaging Sensors V, August 2011.

  48. T. Taha and C. Chen, “Spiking Neural Networks on High Performance Compute Clusters,” SPIE Optics and Photonics for Information Processing V, August 2011.

  49. C. Yakopcic, T. M. Taha, G. Subramanyam, R. E. Pino, and S. Rogers, “Analysis of a Memristor based 1T1M Crossbar Achitecture,” IEEE International Joint Conference on Neural Networks (IJCNN), August 2011 (Invited paper).

  50. K. L. Rice, T. M. Taha, K. M. Iftekharuddin, K. Anderson, and T. Salan, “GPGPU Acceleration of Cellular Simultaneous Recurrent Networks Adapted for Maze Traversals,” IEEE International Joint Conference on Neural Networks (IJCNN), August 2011.

  51. C. Yakopcic, T. M. Taha, G. Subramanyam, and S. Rogers, “Multiple Memristor Read and Write Circuit for Neuromorphic Applications,” IEEE International Joint Conference on Neural Networks (IJCNN), August 2011 (Invited paper).

  52. C. Yakopcic, A. Sarangan, J. Gao, T. M. Taha, G. Subramanyam, and S. Rogers, “TiO2 Memristor Devices,” IEEE National Aerospace & Electronics Conference, July 2011.

  53. T. Messay, C. Chen, R. Ordóñez and T. M. Taha, “GPGPU Acceleration of a Novel Calibration Method for Industrial Robots,” IEEE National Aerospace & Electronics Conference, July 2011.

  54. K. Rice, T. M. Taha, R. Miller, K. M. Iftekharuddin, K. Anderson, and T. Salan, “Accelerating CSRN based face recognition on an NVIDIA GPGPU,” Infotech@Aerospace Conference, March 2011 (Invited paper).

  55. C. Yakopcic, T. M. Taha, G. Subramanyam, E. Shin, P. T. Murray, and S. Rogers, “Memristor-based pattern recognition for image processing: an adaptive coded aperture imaging and sensing opportunity,” Proc. SPIE, Vol. 7818, 78180J, August 2010.

  56. C. Yakopcic, T. M. Taha, G. Subramanyam, E. Shin, P. T. Murray, and S. Rogers, “Memristor Fabrication and Characterization; An Adaptive Coded Aperture Imaging & Sensing Opportunity,” Proc. SPIE, Vol. 7818, 78180J, August 2010.

  57. B. Han and T. M. Taha, “Neuromorphic Models on a GPGPU Cluster,” International Joint Conference on Neural Networks, July 2010.

  58. T. M. Taha, P. Yalamanchili, M. Bhuiyan, R. Jalasutram, C. Chen, and R. Linderman, “Neuromorphic Algorithms on Clusters of PlayStation 3s,” International Joint Conference on Neural Networks, July 2010.

  59. C. Yakopcic, E. Shin, T. M. Taha, G. Subramanyam, P. T. Murray, S. Rogers, “Fabrication and Testing of Memristive Devices,” International Joint Conference on Neural Networks, Barcelona, Spain, July 2010.

  60. M. A. Bhuiyan, V. K. Pallipuram, M. C. Smith, T. M. Taha, R. Jalasutram, “Acceleration of spiking neural networks in emerging multi-core and GPU architectures,” IEEE International Symposium on Parallel & Distributed Processing, April 2010.

  61. P. Yalamanchili and T. M. Taha, “Multicore Cluster Implementations of Hierarchical Bayesian Cortical Models,” International Conference on Computer and Information Technology (ICCIT), December 2009.

  62. K. L. Rice, M. A. Bhuiyan, T. M. Taha, and C. N. Vutsinas, “FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition,” International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, December 2009.

  63. T. M. Taha, P. Yalamanchili, M. A. Bhuiyan, R. Jalasutram, and S. K. Mohan, “Parallelizing Two Classes of Neuromorphic Models on the Cell Multicore Architecture,” IEEE International Joint Conference on Neural Networks (IJCNN), Atlanta, GA, June 2009.

  64. M. A. Bhuiyan, R. Jalasutram, and T. M. Taha, “Character Recognition with Two Spiking Neural Network Models on Multicore Architectures,” IEEE Symposium on Computational Intelligence for Multimedia Signal and Vision Processing (CIMSVP), Nashville, TN, April 2009.

  65. P. Yalamanchili, S. Mohan, and T. Taha, “Implementing a Hierarchical Bayesian Visual Cortex Model on Multi-core Processors,” Proceedings of the 47th Annual Southeast Regional Conference (ACM-SE), Clemson, SC, March 2009.

  66. A. Awwal, K. L. Rice, R. Leach, R., and T. M. Taha, “Higher Accuracy Template for Corner Cube Reflected Image,” Optics and Photonics for Information processing II, San Diego, CA, August 2008.

  67. C. Vutsinas, K. L. Rice, and T. M. Taha “A neocortex model implementation on reconfigurable logic with streaming memory,” Reconfigurable Architectures Workshop (RAW), Miami, FL, April 2008.

  68. K. L. Rice, C. N. Vutsinas, and T. M. Taha, “A Preliminary Investigation of a Neocortex Model Implementation on the Cray XD1,” Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (Supercomputing 2007), Reno, NV, November 2007.

  69. S. Lafontant, and T. M. Taha, “Feasibility of Hardware Acceleration of a Neocortex Model,” Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, June 2007.

  70. C. Smullen, and T. M. Taha, “PSATSim: An Interactive Graphical Superscalar Architecture Simulator for Power and Performance Analysis,” Proceedings of the Workshop on Computer Architecture Education (WCAE), Boston, MA, June 2006.

  71. K. Selvamani, and T. M. Taha, “Estimating Critical Region Parallelism to Guide Platform Retargeting,” Proceedings of the 43rd Annual Southeast Regional Conference (ACM-SE), Atlanta, GA, March 2005.

  72. T. M. Taha, and D. S. Wills, “An Instruction Throughput Model of Superscalar Processors,” Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP), San Diego, CA, June 2003.

  73. L. Wills, T. Taha, L. Baumstark, and D. S. Wills, “Estimating Potential Parallelism for Platform Retargeting,” Proceedings of the 9th Working Conference on Reverse Engineering (WCRE), Richmond, VA, October 2002.

  74. L. Codrescu, M. Deb-Pant, T. Taha, J. Eble, D. S. Wills, and J. Meindl, “Exploring Microprocessor Architectures for Gigascale Integration,” Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI (ARVLSI), Atlanta, GA, March 1999.